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CS5466
DIGITAL CHARACTERISTICS
(Note 7)
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Min / Max characteristics and specifications are guaranteed over all operating conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Characteristics
Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Internal Gate Oscillator
(Note 8 and 9)
MCLK
-
-
3
40
40
4.096
-
-
5
60
60
MHz
%
%
Filter Characteristics
High-pass Filter Corner Frequency
-3 dB
-
-
0.125
-
Hz
Input/Output Characteristics
High-level Input Voltage
V IH
XIN
RESET
(VD+) - 0.5
0.8 ? VD+
-
-
-
-
V
V
Low-level Input Voltage (VD = 5 V)
V IL
XIN
RESET
-
-
-
-
1.5
0.2 ? VD+
V
V
Low-level Input Voltage (VD = 3.3 V)
V IL
XIN
RESET
-
-
-
-
0.3
0.2 ? VD+
V
V
High-level Output Voltage (except XOUT)
Low-level Output Voltage (except XOUT)
Input Leakage Current
Digital Output Pin Capacitance
Drive Current FOUT, E1, E2, NEG
I out = +5 mA
I out = -5 mA
(Note 10)
V OH
V OL
I in
C out
I DR
(VD+) - 1.0
-
-
-
-
-
-
±1
5
50
-
0.4
±10
-
-
V
V
μA
pF
mA
Notes: 7. All measurements performed under static conditions.
8.
9.
10.
DS659F2
If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.
The frequency of CPUCLK is equal to MCLK.
V OL and V OH are not specified under this condition.
7
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